| Course Unit Code | 450-4108/01 |
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| Number of ECTS Credits Allocated | 4 ECTS credits |
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| Type of Course Unit * | Optional |
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| Level of Course Unit * | Second Cycle |
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| Year of Study * | First Year |
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| Semester when the Course Unit is delivered | Winter Semester |
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| Mode of Delivery | Face-to-face |
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| Language of Instruction | Czech |
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| Prerequisites and Co-Requisites | There are no prerequisites or co-requisites for this course unit |
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| Name of Lecturer(s) | Personal ID | Name |
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| KAS73 | Ing. Vladimír Kašík, Ph.D. |
| Summary |
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| The study covers the programmable logic devices design technique, especially of FPGA and CPLD types. An internal architecture is explained in some typical exaples. The design entry techniques include schematic designs, state diagrams and VHDL language. Some specific points of view are discussed: synchronous design, incremental design, hierarchical design, and more. Excercises are aimed to familiarize students with design entry, simulation and implementation tools. The students can verify their results on development boards in lab. |
| Learning Outcomes of the Course Unit |
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The target of this subject is to familiarize students with today's development tools for high performance digital design.The contents of study corresponds with high density, high speed, low power and high reliability requirements of logic devices. The students will be able to choose appropriate development tools for any task and make a required design and implementation of combinatorial and sequential logic functions after passing that course. After that, they will be able to simulate projected design in logic simulator.
simulátoru. They can make the design as schematics, state diagram or VHDL. |
| Course Contents |
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Lectures:
1. Programmable Logic Devices PAL, GAL. Comparison between HW and SW design of logic functions.
2. FPGA Xilinx architecture . Configurable Logic Blocks CLB, IOB, interconnect network.
3. FPGA and CPLD design tools. Introduction to Xilinx ISE development tool, schematic design, VHDL Language.
4. Basic Logic functions design - Logic Gates, Multiplexor, Decoder, Adder, Multiplexor.
5. Basic Sequential logic functions design - D-Flip Flop, Data Register, Shift Register, Counters.
6. Hierarchical Logic Design for FPGA.
7. State diagram as a tool for sequential logic function design. State editor. Applications in Embedded Control Systems.
8. Implementation of memories in FPGA. Block and Distributed RAM.
9. DSP Blocks in FPGA. Utilization in Medical Systems.
10. Design and utilization of IP Macros. Core Generator, EDK.
11. Specific features of FPGA architectures . DCM, HW multipliers...
12. Logic hazards and their elimination. Synchronous and asynchronous logic design.
13. Additional devices for logical system building with FPGA. Power supply and interconnecting devices.
Laboratories:
1. Learning outcomes and competences for credit. Introduction to the Xilinx ISE development environment. Development board Nexys-3, -4. Project \"light snake\".
2. Xilinx ISE Development Environment: Project navigator, schematic design, HDL editor. Synthesis and implementation of the design.
3. Example of combinational logic circuit: arithmetic unit. Specify a separate task.
4. Synchronous design of logic systems, clock signal connection, GBUF driver.
5. Examples of sequential logic circuits. Counter design.
6. Xilinx ISE: Hierarchical design structure, bus, logic simulator, implementation of design. Timing simulation, timing analysis.
7. Implementation of state machine in FPGA. Continuing on a stand-alone task.
8. Xilinx ISE: Implementation of serial interface in FPGA.
9. Continue on a stand-alone task.
10. Continuing on a stand-alone task.
11. Design examples of basic functional blocks. Continuing on a stand-alone task.
12. Continuing on a stand-alone task. Implementation and debugging of a project on a development board.
13. Seminar: Presentation and defense of a separate project, granting of a credit. |
| Recommended or Required Reading |
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| Required Reading: |
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Maxfield, C: The Design Warrior's Guide to FPGAs. Elsevier, 2004. ISBN: 978-0-7506-7604-5
The Programmable Logic Databook , Xilinx Inc., 1999.
Parnell, K. – Mehta, N.: Programmable Logic Design Quick Start Handbook. 4th ed. [s.l.]: Xilinx Inc., 2003. 225 s.
Ashenden, P.J. The Designer's Guide to VHDL. San Francisco(USA): Morgan Kaufmann Publishers, 1999. 688 s. ISBN 1-55860-270-4. |
Kašík, V.: Programování hradlových polí. Učební text a návody do cvičení. VŠB-TUO, FEI, 2012.
Šťastný, J.: FPGA prakticky. BEN - technická literatura, 2011. ISBN: 978-80-7300-261-9.
Pinker, J. – Poupa, M.: Číslicové systémy a jazyk VHDL. BEN - technická literatura, 2006. ISBN: 80-7300-198-5.
Parnell, K. – Mehta, N.: Programmable Logic Design Quick Start Handbook. 4th ed. [s.l.]: Xilinx Inc., 2003. 225 s.
Ashenden, P.J.: The Designer's Guide to VHDL. San Francisco(USA): Morgan Kaufmann Publishers, 1999. 688 s. ISBN 1-55860-270-4. |
| Recommended Reading: |
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Berge, J.: VHDL Designer's Reference. Dordrecht, Kluwer Academic, 1992.
Mirkowski, J. - Kapustka,M. - Skowroński, Z. - Biniszkiewicz, A.: EVITA Interactive VHDL Tutorial REV.2.1. Henderson, ALDEC, Inc., 1998.
Kilts, S.: Advanced FPGA Design. John Wiley and Sons Ltd, 2007. ISBN: 9780470054376. |
The Programmable Logic Databook , Xilinx Inc., 1999.
Bernard, J.B. - Hugon, J. - Le Corvec, R.: Od logických obvodů k mikroprocesorům. SNTL, Praha, 1988.
Berge, J.: VHDL Designer's Reference. Dordrecht, Kluwer Academic, 1992.
Mirkowski, J. - Kapustka,M. - Skowroński, Z. - Biniszkiewicz, A.: EVITA Interactive VHDL Tutorial REV.2.1. Henderson, ALDEC, Inc., 1998.
Kilts, S.: Advanced FPGA Design. John Wiley and Sons Ltd, 2007. ISBN: 9780470054376. |
| Planned learning activities and teaching methods |
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| Lectures, Individual consultations, Experimental work in labs, Project work |
| Assesment methods and criteria |
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| Task Title | Task Type | Maximum Number of Points
(Act. for Subtasks) | Minimum Number of Points for Task Passing |
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| Credit and Examination | Credit and Examination | 100 (100) | 51 |
| Credit | Credit | 40 | 20 |
| Examination | Examination | 60 | 30 |