Lectures:
Integrated development system, stage of design
Basic elements of VHDL language - entity,architecture.
Statements of VHDL language, declaration, object of VHDL, data types.
Statements of VHDL language, dataflow programming,
Statements of VHDL language, sequence programming
Statements of VHDL language, structural modeling
Description of combination and sequence logic circuite
Programmable logic devices, basic notation.
Programmable logic devices, PROM, PLA, PAL and GAL.
Fundamental blocks of CPLD and FPGA.
System characteristics of PLD.
Programmable logic devices, CPLD and FPGA.
Characteristics of PLD.
Analog PLD.
SoC - system on chip.
Projects:
Design of combinational logic circuit.
Design of sequence logic circuit.
Realization of design.
Computer labs:
Integrated development environment.Tutorial.
Integrated development environment.
Integrated development environment.
Assign design no.1 - design combinational circuits. Assign work no. 3 - realization design in PLD.
Solution of individual design no.1.
Solution of individual design no.1.
Realization of design in PLD.
Assign design no.2.
Solution of individual design no.2.
Solution of individual design no.2.
Integrated development system, stage of design
Basic elements of VHDL language - entity,architecture.
Statements of VHDL language, declaration, object of VHDL, data types.
Statements of VHDL language, dataflow programming,
Statements of VHDL language, sequence programming
Statements of VHDL language, structural modeling
Description of combination and sequence logic circuite
Programmable logic devices, basic notation.
Programmable logic devices, PROM, PLA, PAL and GAL.
Fundamental blocks of CPLD and FPGA.
System characteristics of PLD.
Programmable logic devices, CPLD and FPGA.
Characteristics of PLD.
Analog PLD.
SoC - system on chip.
Projects:
Design of combinational logic circuit.
Design of sequence logic circuit.
Realization of design.
Computer labs:
Integrated development environment.Tutorial.
Integrated development environment.
Integrated development environment.
Assign design no.1 - design combinational circuits. Assign work no. 3 - realization design in PLD.
Solution of individual design no.1.
Solution of individual design no.1.
Realization of design in PLD.
Assign design no.2.
Solution of individual design no.2.
Solution of individual design no.2.