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Terminated in academic year 2022/2023

Programmable Logic Devices

Type of study Follow-up Master
Language of instruction Czech
Code 450-4029/03
Abbreviation PHP
Course title Programmable Logic Devices
Credits 4
Coordinating department Department of Cybernetics and Biomedical Engineering
Course coordinator Ing. Vladimír Kašík, Ph.D.

Subject syllabus

Lectures:
1. Programmable Logic Devices PAL, GAL. Comparison between HW and SW design of logic functions.
2. FPGA Xilinx architecture . Configurable Logic Blocks CLB, IOB, interconnect network.
3. FPGA and CPLD design tools. Introduction to Xilinx ISE development tool, schematic design, VHDL Language.
4. Basic Logic functions design - Logic Gates, Multiplexor, Decoder, Adder, Multiplexor.
5. Basic Sequential logic functions design - D-Flip Flop, Data Register, Shift Register, Counters.
6. Hierarchical Logic Design for FPGA.
7. State diagram as a tool for sequential logic function design. State editor. Applications in Embedded Control Systems.
8. Implementation of memories in FPGA. Block and Distributed RAM.
9. DSP Blocks in FPGA. Utilization in Medical Systems.
10. Design and utilization of IP Macros. Core Generator, EDK.
11. Specific features of FPGA architectures . DCM, HW multipliers...
12. Logic hazards and their elimination. Synchronous and asynchronous logic design.
13. Additional devices for logical system building with FPGA. Power supply and interconnecting devices.

Laboratories:

1. Learning outcomes and competences for credit. Introduction to the Xilinx ISE development environment. Development board Nexys-3, -4. Project \"light snake\".
2. Xilinx ISE Development Environment: Project navigator, schematic design, HDL editor. Synthesis and implementation of the design.
3. Example of combinational logic circuit: arithmetic unit. Specify a separate task.
4. Synchronous design of logic systems, clock signal connection, GBUF driver.
5. Examples of sequential logic circuits. Counter design.
6. Xilinx ISE: Hierarchical design structure, bus, logic simulator, implementation of design. Timing simulation, timing analysis.
7. Implementation of state machine in FPGA. Continuing on a stand-alone task.
8. Xilinx ISE: Implementation of serial interface in FPGA.
9. Continue on a stand-alone task.
10. Continuing on a stand-alone task.
11. Design examples of basic functional blocks. Continuing on a stand-alone task.
12. Continuing on a stand-alone task. Implementation and debugging of a project on a development board.
13. Seminar: Presentation and defense of a separate project, granting of a credit.

Literature

Maxfield, C: The Design Warrior's Guide to FPGAs. Elsevier, 2004. ISBN: 978-0-7506-7604-5 
The Programmable Logic Databook , Xilinx Inc., 1999.
Parnell, K. – Mehta, N.: Programmable Logic Design Quick Start Handbook. 4th ed. [s.l.]: Xilinx Inc., 2003. 225 s.
Ashenden, P.J. The Designer's Guide to VHDL. San Francisco(USA): Morgan Kaufmann Publishers, 1999. 688 s. ISBN 1-55860-270-4 .

Advised literature

Berge, J.: VHDL Designer's Reference. Dordrecht, Kluwer Academic, 1992.
Mirkowski, J. - Kapustka,M. - Skowroński, Z. - Biniszkiewicz, A.: EVITA Interactive VHDL Tutorial REV.2.1. Henderson, ALDEC, Inc., 1998.
Kilts, S.: Advanced FPGA Design. John Wiley and Sons Ltd, 2007. ISBN: 9780470054376.