Languages for Designing HDL (Hardware Design Language)

Application of Hardware Design Languages (HDL = VHDL or Verilog), which are generally accepted as means of description, is a good way for design, simulation and implementation of Application Specific Integrated Circuits (ASIC). The HDL is actually necessary and obvious part of description of computer systems, due to economics enhancement as well as computer reliability. The methodology makes better computer reliability and innovation cycle shortening of application units. The language for design automation Very High-Speed Integrated Circuits Hardware Description Language (VHDL) is a basic mean, which makes possible to design applications of computer units in the form of modern electronic circuits on the basis of project documentation of boards with programmable elements CPLD, FPGA a FPAA. The support of the design contains circuit verification by simulation on the behavioural, data flow or structure levels. Non-dividing part of the circuit design is the test design, which is supported by Boundary Scan Design Language (BSDL), which can was defined as so called B-Supplement of the VHDL. The exercises of the course are supported by professional program environment GALILEO of Mentor Graphics under operational system UNIX, which run on the workstations APOLLO. The user environment of interactive design ACTIVE CAD and ACTIVE VHDL of Aldec deliver another program support.